A number of years in the past I wrote an article in Design Concepts referred to as “Double µC’s PWM frequency & decision” the place I discussed how one can lower the output ripple of a PWM-based DAC utilizing two PWM indicators having equal obligation cycles with 180-degree part (half a interval delay) distinction with one another.
The thought behind the PWM DAC is kind of easy: it’s to filter out the entire harmonic content material of the PWM sign and be left with solely the DC part of it. To attain this, the PWM sign is low-pass filtered. Clearly when you’ve a filter with a decrease cut-off frequency the output goes to be much more “ripple-less,” however the transient response goes to be very gradual or vice versa.
The concept that was offered within the aforementioned article was to generate an anti-phase sign to cancel out a number of the harmonic elements by part cancellation motion quite than relying purely on the filter itself.
This concept turned out to be helpful in lowering the ripple while additionally bettering the transient response. Nevertheless, its usefulness is sort of restricted as a result of not the entire harmonic elements of the PWM indicators have been cancelling one another out. To be extra particular, solely odd harmonics are cancelling one another and even harmonics are solely affected by the filter as a result of once we introduce half a interval delay solely odd harmonics experiences 180-degree part shift and even harmonics goes via 360-degree part shift which is similar as being in part. That ends in even harmonics not cancelling one another out.
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The truth is, for 50% obligation cycle (it incorporates solely odd harmonics) we get ripple-free output utilizing this method. For some other obligation cycle there’s going to be some ripple, however there’s nonetheless going to be some enchancment in ripple amplitude in comparison with its single channel equal. We will increase this concept by utilizing extra PWM channels with completely different part variations to get extra ripple-less obligation cycles factors.
Let’s say we determined to make use of n channels at f Hz, if every consecutive PWM channel has 1/(f.n) delay (or 360/n part shift) with respect to one another then each harmonic elements goes to be cancelled due to evenly spaced time delays besides for each nth harmonic. To be clearer, let’s say we’re utilizing 10 kHz as our essential PWM frequency and we implement 4 channels with 25µs time delay (90-degree part shift). In that case, the primary channel is our base channel and it doesn’t have delay; the second channel has 25µs delay(90-degree) with respect to the bottom channel; the third channel has 50µs delay(180-degree) with respect to the bottom channel; and the final channel has 75µs delay (270-degree) with respect to the bottom channel.
As said earlier every consecutive channel has 25µs (1/(f.n), f=10kHz, n=4) delay with respect to its “neighboring” channel. This circuit is proven in Determine 1 together with the one-channel and two-channel variations.
Determine 1 The four-channel phased-array PWM DAC circuit together with the one- and two-channel variations.
The output of this four-channel PWM DAC goes to include solely the 4th harmonic of the bottom PWM frequency, and in consequence the output goes to include no ripple when the obligation cycle is 25%, 50% or 75% as a result of these PWM indicators don’t have any 4th harmonic content material.
In Figures 2, 3 and 4 we are able to see the outputs of every circuit with obligation cycles of 25%, 50% and 75%, respectively.
Determine 2 The circuit with 25% obligation cycle.
Determine 3 The circuit with 50% obligation cycle.
Determine 4 The circuit with 75% obligation cycle.
As anticipated at 25% obligation cycle output of the four-channel circuit (darkish blue) has nearly no ripple and has the quickest transient response; the two-channel circuit (pink) has ripple, however its ripple is lower than the one channel’s (gentle blue) circuit output and it’s sooner. At 50% each the two-channel circuit (pink) and four-channel circuit (darkish blue) don’t have any ripple, however the four-channel circuit has sooner transient response and clearly the one channel (gentle blue) circuit is slowest and noisiest. And for 75% the outcomes are the identical as 25%.
For testing, the circuits are applied in VHDL utilizing FPGA (GitHub hyperlink is shared on the finish of the publish) as a result of there have been many channels and this concept might be additional expanded by deploying much more channels. Typically talking, if n channels are applied, there are going to be n-1 ripple-less obligation cycle factors (excluding 0% and 100% that are inherently ripple-less). Theoretically, an 8-bit DAC might be applied utilizing 256 channels with this methodology, however after all that’s going to be extremely impractical, however nobody can cease you having fun with the thought. ?
For the sake of completeness, this methodology is simulated in LTSpice as much as eight channels (additionally within the GitHub hyperlink on the finish of the publish). From the identical reasoning, for an eight-channel circuit you must get ripple-free output at multiples of 12.5% obligation cycle factors; you’ll be able to see it your self by downloading the LTSpice file. In the identical means in case you implement 100 channels you get ripple-less output at each a number of of 1% obligation cycle.
In conclusion, by deploying extra PWM channels with acceptable evenly spaced part delays one can obtain ripple-less output at sure obligation cycles and even at random obligation cycles one can nonetheless enhance each transient response and noise efficiency, which isn’t doable with a classical single-channel PWM DAC strategy.
GitHub hyperlink: https://github.com/AlperenAkk/PWM_phased_array_DAC
— Alperen Akküncü is an electronics design engineer/scholar dwelling in Turkey, with pursuits in precision analog circuitry, embedded techniques, and FPGAs.
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